Filter
Top Products
Full-size CPU Card FSB- 865G
Appendix B Programming the Watchdog Timer B-4
WatchDog Timer Register I (Index=F5h, Default=00h)
CRF5 (PLED mode register. Default 0 x 00)
Bit 7-6 : select PLED mode
= 00 Power LED pin is tri-stated.
= 01 Power LED pin is drived low.
= 10 Power LED pin is a 1Hz toggle pulse with
50 duty cycle.
= 11 Power LED pin is a 1/4Hz toggle pulse
with 50 duty cycle.
Bit 5-4 : Reserved
Bit 3 : select WDTO count mode.
= 0 second
= 1 minute
Bit 2 : Enable the rising edge of keyboard Reset (P20) to
force Time-out event.
= 0 Disable
= 1 Enable
Bit 1-0 : Reserved
WatchDog Timer Register II (Index=F6h, Default=00h)
Bit 7-0 = 0 x 00 Time-out Disable
= 0 x 01 Time-out occurs after 1
second/minute
= 0 x 02 Time-out occurs after 2
second/minutes
= 0 x 03 Time-out occurs after 3