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Intel® Solid-State Drive 530 Series (mSATA)
Product Specification September 2013
16 Order Number: 329280-002US
Table 11. Serial ATA Power Pin Definitions
Pin
1
Function Definition
P33 +A Host Transmitter Differential Signal Pair (This is an input of the SSD)
P34 GND Ground
P35 GND Ground
P36 Reserved No Connect
P37 GND Ground
P38 Reserved No Connect
P39 +3.3 V 3.3 V Source
P40 GND Ground
P41 +3.3 V 3.3 V Source
P42 Reserved No Connect
P43 Device Type No Connect
P44 DevSleep Device Sleep pin
P45
3
Vendor Vendor Specific / Manufacturing Pin
P46 Reserved No Connect
P47
3
Vendor Vendor Specific / Manufacturing Pin
P48
1
+1.5 V 1.5 V Source
P49 DAS/DSS Device Activity Signal / Disable Staggered Spin-up
P50 GND Ground
P51
4
Presence Detection Shall be pulled to GND by device
P52 +3.3 V 3.3 V Source
Note:
1. 1.5 V rail is not used on the Intel SSD 530 Series. No connect on the host side. Pin 6, 28, and 48 shall be unconnected on
the device side to avoid conflicts with wireless coexistence pins as specified in PCI Express Mini Card Specification.
3. Pins 30 and 32 are intended for use as a two-wire interface to read a memory device to determine device information (an
example of this would be for use as SMB bus pins). These pins are not designed to be active in conjunction with the SATA
signal differential pairs. Not used on the Intel SSD 530 Series. No connect on the host side.
3. Vendor-specific pins are not used in the Intel SSD 530 Series. No connect on the host side.
4. Presence detection pin indicates presence of an mSATA device.
4.3 Device Sleep Feature
Device Sleep (or DevSleep/DEVSLP) is a new platform feature aligned with the mobile Intel® 4th
Generation Core™ Processor. Many new mobile computing platforms, such as Ultrabooks™, have
stringent power requirements for SSDs and require an ability to put the drive in a low power state.
Although Link Power Management allows some control over power consumption, both methods still
require the SATA link to remain online. The DevSleep pin is an enable high pin.