![](http://pdfasset.owneriq.net/9/60/96084fff-d3f8-4412-8a76-b7f8937e4a75/96084fff-d3f8-4412-8a76-b7f8937e4a75-bg27.png)
AT INTERFACE DESCRIPTION
5 – 9
DMARQ
(device)
DMACK-
(host)
STOP
(host)
DDMARDY-
(device)
HSTROBE
(host)
DD(15:0)
(host)
t
SR
t
RFS
t
RP
Figure 5 - 11
Device Pausing an Ultra DMA Data Out Burst
DMARQ
(device)
DMACK-
(host)
STOP
(host)
DDMARDY-
(device)
HSTROBE
(host)
DD(15:0)
(host)
DA0, DA1, DA2,
CS0-, CS1-
t
ACK
t
LI
t
MLI
t
DVS
t
LI
t
LI
t
ACK
t
IORDYZ
t
ACK
CRC
t
DVH
t
SS
Figure 5 - 12
Host Terminating an Ultra DMA Data Out Burst