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Chapter 3
3-14
DRAM Timing by SPD
The field decides whether DRAM timing is configured by reading the
contents of the SPD (Serial Presence Detect) device on the DRAM
module. Setting to Enabled makes DRAM Frequency(MHz), DRAM
CAS Latency, Bank Interleave, Row Precharge, RAS Pulse, RAS to
CAS and Burst Length automatically determined by BIOS according to
the configurations on the SPD.
DRAM Frequency(MHz)
The chipset supports synchronous and asynchronous mode between
host clock and DRAM clock frequency. The settings are:
HCLK The DRAM clock will be equal to the Host Clock.
HCLK-33 The DRAM clock will be equal to the Host Clock
minus 33MHz. For example, if the Host Clock is
133MHz, the DRAM clock will be 100MHz.
HCLK+33 The DRAM clock will be equal to Host Clock plus
33MHz. For example, if the Host Clock is 100MHz,
the DRAM clock will be 133MHz.
Auto BIOS automatically determines the DRAM clock
frequency.
DRAM CAS Latency
The item controls the timing delay (in clock cycles) before SDRAM
starts a read command after receiving it. Settings: Auto, 2, 2.5 and 3. 2
increases system performance while 3 provides more stable system
performance.
Bank Interleave
The item is used to enable or disable bank interleave feature. Settings:
Auto and Disabled.
Row Precharge
This setting allows you to select the number of DRAM clocks allocated
for the Row Address Strobe (RAS#) signal to accumulate its charge
before the DRAM is refreshed. If insufficient time is allowed, refresh
may be incomplete and data lost. The less the clock cycles, the faster
the DRAM performance. Settings: 3T, 2T and Auto.