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© National Instruments Corporation 3-1 MXI-4 Series User Manual
3
Hardware and Software
Overview
This chapter presents an overview of the hardware and software function of
MXI-4 cards, and explains the operation of each functional unit.
Hardware Overview
Functional Overview
The PCI specification places a limit on the number of PCI devices that can
be placed on any single PCI bus segment in order to guarantee the electrical
characteristics and timing of the bus. This limitation spawned the need for
devices that could logically couple electrically independent busses to form
a hierarchical PCI system. The PCI Special Interest Group recognized this
need and created the PCI-PCI Bridge Architecture Specification in 1994 to
provide a standardized register set and well defined functionality for such
devices.
Each MXI-4 dyad implements this PCI-PCI Bridge Architecture
Specification for the purpose of coupling PCI-based peripherals located in
separate chassis into a single PCI hierarchy. Each of the MXI-4 cards
contains half of the bridge logic, and uses the serial link to communicate
between those two halves at a maximum rate of 1.5 Gbits/sec.
Using the PCI-PCI Bridge specification as the basis for its implementation
allows MXI-4 to connect a large number of peripheral devices while
allowing them to use the same drivers that would be used if they were in the
host system. This is possible because the PCI-PCI Bridge Architecture
Specification was designed to be transparent to device drivers, and because
all major operating systems and BIOSes support configuration of the
bridges natively.
Figure 3-1 shows the basic architecture of a MXI-4 card. The MXI-4 FPGA
is connected to the PCI bus, a serializer and a deserializer. The serializer
and deserializer then connect to either a fiber-optic transceiver, which
converts the electrical signals to laser-light and vice versa, or directly