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Chapter 4 Award BIOS Setup
EB-471LF USER
′
S MANUAL
Page: 4-11
DRAM TIMING BY SELECTABLE:
This allows you to select the DRAM timing.
CAS LATENCY TIME:
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing.
ACTIVE TO PRECHARGE DELAY:
This item controls the number of DRAM clocks for TRAS.
DRAM RAS# TO CAS# DELAY:
This field let’s you insert a timing delay between the CAS and RAS strobe
signals, used when DRAM is written to, read from, or refreshed. Fast gives
faster performance; and Slow gives more stable performance. This field
applies only when synchronous DRAM is installed in the system.
DRAM RAS# PRECHARGE:
If an insufficient number of cycles is allowed for the RAS to accumulate its
charge before DRAM refresh, the refresh may be incomplete and the DRAM
may fail to retain data. Fast gives faster performance; and Slow gives more
stable performance. This field applies only when synchronous DRAM is
installed in the system.
DRAM DATA INTEGRITY MODE:
Select Parity or ECC (error-correcting code), according to the type of installed
DRAM.
SYSTEM BIOS CACHEABLE:
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any program
writes to this memory area, a system error may result.
VIDEO BIOS CACHEABLE:
Select Enabled allows caching of the video BIOS, resulting in better system
performance. However, if any program writes to this memory area, a system
error may result.