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MuxOneNAND2G(KFM2G16Q2A-DEBx)
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MuxOneNAND4G(KFN4G16Q2A-DEBx)
6.18 Warm Reset Timing
See AC Characteristics Tables 5.6.
NOTE :
1) The status which can accept any register based operation(Load, Program, Erase command, etc.).
2) The status where reset is ongoing.
3) The status allows only BootRAM(BL1) read operation for Boot Sequence.(refer to 7.2.2 Boot Sequence)
4) To read BL2 of Boot Sequence, Host should wait INT until becomes ready. and then, Host can issue load command.
(refer to 7.2.2 Boot Sequence, 7.1 Methods of Determining Interrupt status)
CE, OE
RP
tRP
tReady1
RDY
INT
High-ZHigh-Z
tReady2
Idle
1)
Operation
Status
Reset Ongoing
2)
BootRAM Access
3)
Idle
1)
INT Bit Polling
4)
bit