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You can disable both the Write Reallocation and write cache using value
82
H
. These two features coexists as a pair and are enabled/disabled
together.
3.3 Synchronous DMA Transfer
3.3.1 Signal Line Definitions
Some existing ATA signal lines are redefined during the Synchronous
DMA protocol to provide new functions. If the Synchronous DMA transfer
mode was previously chosen by the Set Features, the ATA lines change
from the old to new definitions as soon as the host allows for a DMA
burst. The drive detects this change when the –DMACK line is asserted.
These lines revert back to their original definitions upon the de-assertions
of –DMACK at the termination of the DMA burst.
Signal Line Definitions
New Definitions Old Definitions
DMARQ DMARQ
–DMACK –DMACK
–DMACK IORDY on write commands
–DIOR on read commands
STROBE –DIOR on write commands
IORDY on read commands
STOP –DIOW
Note.
DMARQ and –DMACK signal lines remain unchanged. This en-
sures backward-compatibility with PIO modes.
3.3.2 Protocol Rules
The general rules of the Synchronous DMA Transfer Protocol are as
follows:
• A DMA burst is defined as the period from an assertion of –DMACK
to subsequent de-assertion of –DMACK.
• A receiver must be prepared to receive at least two words of data
whenever it enters or resumes a burst mode.
Medalist Pro 6450/6451 Product Manual, Rev. B 35