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CORTEX A-8 : Highlights
• First ARMv7 instruction-set architecture
• Superscalar architecture delivers high performance
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Advanced dynamic Branch prediction
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Advanced dynamic Branch prediction
• 256 KB unified L2 cache
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Dedicated, low
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latency, high
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BW interface to L1 cache
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Dedicated, low
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latency, high
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BW interface to L1 cache
• Enhanced VFPv3
– Doubles number of double-precision registers
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Adds new instructions to convert between fixed and floating point
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Adds new instructions to convert between fixed and floating point
• Efficient Run Time Compilation Target
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Jazelle
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RCT: Target for Java. Memory footprint reduced up to 3x
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Jazelle
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RCT: Target for Java. Memory footprint reduced up to 3x
• Trust Zone
– Normal & Secure worlds have different memory views
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