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44
Chapter 3
BIOS Configuration
Chipset Features Setup - Default Settings Chart
Bank 0/1, 2/3, 4/5 DRAM Timing
The system board designer must select the proper value for these fields,
according to the specifications of the installed DRAM chips. Turbo mode
reduces CAS access time by 1 clock tick.
SDRAM Cycle Length
This field sets the CAS latency timing.
DRAM Read Pipeline
Select Enabled to pipeline reads from system memory. Pipelining improves
system performance.
Cache Rd+CPU Wt Pipeline
Select Enabled to pipeline reads from cache memory and writes from the CPU.
Pipelining improves system performance.
Setting Option BIOS Default Setup Default
Ba nk 0 /1 DRA M Timin g SDRA M 10 ns S DRA M 10n s
B ank 2/3 D R AM T i min g F P/ED O 7 0ns F P/ED O 70n s
B ank 4/5 D R AM T i min g F P/ED O 7 0ns F P/ED O 70n s
SDRAM Cycle Length 3 3
DRAM Read Pipeline Disabled Enabled
Cache Rd+CPU Wt Pipeline Disabled Enabled
Cache Timing Fast Fast
Video BIOS Cacheable Disabled Enabled
System BIOS Cacheable Disabled Enabled
Memory Hole At 15Mb Addr Disabled Disabled
AGPAperture Size 64M 64M
OnChip US B Ena bled Enab le d
USB Keyboard Support Disabled Disabled
Current CPU Temperature 35C / 95F 35C / 95F
Current System Temp. 27C / 80F 27C / 80F
Current CPUFAN Speed 0 RPM 0 RPM
Current SYSFAN Speed 0 RPM 0 RPM
Vcore 2.40V 2.40V
3.3V 3.31V 3.31V
5V 4.95V 4.95V
12V 12.12V 12.12V