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PCI32 Interface v3.0
DS206 August 31, 2005 www.xilinx.com 9
Product Specification v3.0.151
Table 4: Timing Parameters, 66 MHz Implementations
Symbol Parameter Min Max
T
cyc
CLK Cycle Time 15
1
30
T
high
CLK High Time 6 -
T
low
CLK Low Time 6 -
T
val
CLK to Signal Valid Delay
(bussed signals)
2
2
6
2
T
val
CLK to Signal Valid Delay
(point to point signals)
2
2
6
2
T
on
Float to Active Delay 2
2
-
T
off
Active to Float Delay - 14
1
T
su
Input Setup Time to CLK
(bussed signals)
3
2,3
-
T
su
Input Setup Time to CLK
(point to point signals)
5
2,3
-
T
h
Input Hold Time from CLK 0
2,3
-
T
rstoff
Reset Active to Output Float - 40
Notes
1. Controlled by timespec constraints, included in product.
2. Controlled by SelectIO configured for PCI66_3.
3. Controlled by guide file, included in product.
Table 5: Timing Parameters, 33 MHz Implementations
Symbol Parameter Min Max
T
cyc
CLK Cycle Time
30
1
-
T
high
CLK High Time 11 -
T
low
CLK Low Time 11 -
T
val
CLK to Signal Valid Delay
(bussed signals)
2
2
11
2
T
val
CLK to Signal Valid Delay
(point to point signals)
2
2
11
2
T
on
Float to Active Delay 2
2
-
T
off
Active to Float Delay - 28
1
T
su
Input Setup Time to CLK
(bussed signals)
7
2
-
T
su
Input Setup Time to CLK
(point to point signals)
10
2
-
T
h
Input Hold Time from CLK 0
2
-
T
rstoff
Reset Active to Output Float - 40
Notes
1. Controlled by timespec constraints, included in product.
2. Controlled by SelectIO configured for PCI33_3 or PCI33_5.