PRELIMINARY
CY14B108L, CY14B108N
Document #: 001-45523 Rev. *B Page 23 of 24
Document History Page
Document Title: CY14B108L/CY14B108N 8 Mbit (1024K x 8/512K x 16) nvSRAM
Document Number: 001-45523
Rev. ECN No. Orig. of Change
Submission
Date
Description of Change
** 2428826 GVCH See ECN New Data Sheet
*A 2520023 GVCH/PYRS 06/23/08 Updated I
CC1
for tRC=20ns, 25ns and 45ns access speed for both industrial
and Commercial temperature Grade
Updated Thermal resistance values for 48-FBGA,44-TSOP II and 54-TSOP II
packages
Changed t
CW
value from 16ns to 15ns
*B 2676670 GVCH/PYRS 03/20/2009 Added maximum accumulated storage time for 150°C and 85°C Temperature
Added best practices
Changed I
CC2
from 12mA to 20mA
Changed I
CC3
from 38mA to 40mA
Changed I
CC4
from 12mA to 10mA
Changed I
SB
from 6mA to 10mA
Changed V
CAP
from 164uF to 360uF
Changed Input Rise and Fall Times from 5ns to 3ns
Updated I
CC1
, I
CC3
, I
SB
and I
OZ
Test conditions
Changed t
DELAY
to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively
Changed t
STORE
from 15ms to 8ms
Added V
HDIS
, t
HHHD
and t
LZHSB
parameters
Software controlled STORE/RECALL cycle table: Changed t
AS
to t
SA
Changed t
GHAX
to t
HA
Added t
DHSB
parameter
Changed t
HLHX
to t
PHSB
Updated t
SS
from 70us to 100us
Added Truth table for SRAM operations
Updated ordering information
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