Document Number: 001-52037 Rev. ** Page 6 of 17
SRAM WRITE Cycle #1 and #2
NO.
Symbols
Parameter
STK14D88-25 STK14D88-35 STK14D88-45
Unit
Min Max Min Max Min Max#1 #2 Alt.
12 t
AVAV
t
AVAV
t
WC
Write Cycle Time 25 35 45 ns
13 t
WLWH
t
WLEH
t
WP
Write Pulse Width 20 25 30 ns
14 t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write 20 25 30 ns
15 t
DVWH
t
DVEH
t
DW
Data Set-up to End of Write 10 12 15 ns
16 t
WHDX
t
EHDX
t
DH
Data Hold after End of Write 0 0 0 ns
17 t
AVWH
t
AVEH
t
AW
Address Set-up to End of Write 20 25 30 ns
18 t
AVWL
t
AVEL
t
AS
Address Set-up to Start of Write 0 0 0 ns
19 t
WHAX
t
EHAX
t
WR
Address Hold after End of Write 0 0 0 ns
20 t
WLQZ
[6, 8]
t
WZ
Write Enable to Output Disable 10 13 15 ns
21 t
WHQX
t
OW
Output Active after End of Write 3 3 3 ns
Figure 6. SRAM WRITE Cycle 1: W
Controlled
[8, 9]
Figure 7. SRAM WRITE Cycle 2: E Controlled
[8, 9]
DATA OUT
E
ADDRESS
W
DATA IN
PREVIOUS DATA
12
t
AVAV
13
t
WHDX
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVWH
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
12
t
AVAV
16
t
EHDX
13
t
WLEH
19
t
EHAX
18
t
AVEL
17
t
AVEH
DATA VALID
15
t
DVEH
HIGH IMPEDANCE
14
t
ELEH
DATA OUT
E
ADDRESS
W
DATA IN
Notes
8. If W
is low when E goes low, the outputs remain in the high-impedance state.
9. E
or W must be ≥ V
IH
during address transitions.
[+] Feedback
