134 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
SRL [%ir] Shift right location [ir reg.] logical 2 cycles
Function:
Shifts the content of the data memory addressed by the ir register (X or Y) to the right for 1 bit.
Bit 0 of the r register moves to the C flag and bit 3 goes "0".
Code:
Mnemonic MSB LSB
SRL [%X] 100001110010010E4H
SRL [%Y] 100001110011010E6H
Flags: EICZ
↓ – ↕↕
Mode: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: SRL [%X] Shifts the content of [00imm8] (00imm8 = 0000H + 00H to FFH)
LDB %EXT,imm8
SRL [%Y] Shifts the content of [FFimm8] (FFimm8 = FF00H + 00H to FFH)
SRL [%ir]+ Shift right location [ir reg.] logical and increment ir reg. 2 cycles
Function: , ir ← ir + 1
Shifts the content of the data memory addressed by the ir register (X or Y) to the right for 1 bit.
Bit 0 of the r register moves to the C flag and bit 3 goes "0". Then increments the ir register (X
or Y). The increment result of the ir register does not affect the flags.
Code:
Mnemonic MSB LSB
SRL [%X]+ 100001110010110E5H
SRL [%Y]+ 100001110011110E7H
Flags: EICZ
↓ – ↕↕
Mode: Register indirect
Extended addressing: Invalid
[ir]
C
32100
[ir]
C
32100
