Intel® Solid-State Drive DC P3700 Series
Product Specification May 2015
22 330566-009US
Table 17: Pin Definition for Add-In Card (Half Height Half Length) Form Factor
SMBus(System Management Bus) clock
TCK (Test Clock), clock input for JTAG
interface
SMBus (System Management Bus) data
TRST# (Test Reset) resets the JTAG interface
Signal for Link reactivation
Reference clock (differential pair)
Transmitter differential pair, Lane 0
Reference clock (differential pair)
Transmitter differential pair, Lane 0
Receiver differential pair, Lane 0
Receiver differential pair, Lane 0
Transmitter differential pair, Lane 1
Transmitter differential pair, Lane 1
Receiver differential pair, Lane 1
Receiver differential pair, Lane 1
Transmitter differential pair, Lane 2
Transmitter differential pair, Lane 2
Receiver differential pair, Lane 2
Receiver differential pair, Lane 2
Transmitter differential pair, Lane 3
Transmitter differential pair, Lane 3
Receiver differential pair, Lane 3
Receiver differential pair, Lane 3
NOTES:
All pins are numbered in ascending order from the left to the right, with side A on the top of the centerline and
side B on the bottom of the centerline, use the reference drawing in Fig2, with the logo visible.
The PCI Express interface pins PETpx, PETnx, PERpx, and PERnx are named with the following convention: “PE”
stands for PCI Express high speed, “T” for Transmitter, “R” for Receiver, “p” for positive (+) and “n” for negative (-).
The sequential mating for Hot-Plug is accomplished by staggering the edge fingers on the add-in card.
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