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Chapter 4 147
POST Code Reference Tables
These tables describe the POST codes and components of the POST process.
Post Code Range
SEC Phase POST Code Table
NOTE: The color bar items indicate 3rd party related functions that are platorm dependent.
PEI Phase POST Code Table:
Phase POST Code Range
SEC 0x01 - 0x0F
PEI 0x70 - 0x9F
DXE 0x40 - 0x6F
BDS 0x10 - 0x3F
SMM 0xA0 - 0xBF
S3 0xC0 - 0xCF
ASL 0x51 – 0x55
0xE1 – 0xE4
PostBDS 0xF9 – 0xFE
InsydeH2ODDT™
Reserve
0xD0 – 0xD7
OEM Reserve 0xE8 – 0xEB
Reserved 0xD8 – 0xE0
0xE5 – 0xE7
0xEC – 0xF8
Functionality Name (Include\
PostCode.h)
Phase
Post
Code
Description
SEC_SYSTEM_POWER_ON SEC 1 CPU power on and switch to
Protected mode
SEC_BEFORE_MICROCODE_PATCH SEC 2 Patching CPU microcode
SEC_AFTER_MICROCODE_PATCH SEC 3 Setup Cache as RAM
SEC_ACCESS_CSR SEC 4 PCIE MMIO Base Address initial
SEC_GENERIC_MSRINIT SEC 5 CPU Generic MSR initialization
SEC_CPU_SPEEDCFG SEC 6 Setup CPU speed
SEC_SETUP_CAR_OK SEC 7 Cache as RAM test
SEC_FORCE_MAX_RATIO SEC 8 Tune CPU frequency ratio to
maximum level
SEC_GO_TO_SECSTARTUP SEC 9 Setup BIOS ROM cache
SEC_GO_TO_PEICORE SEC 0A Enter Boot Firmware Volume
Functionality Name (Include\
PostCode.h)
Phase
Post
Code
Description
PEI_SIO_INIT PEI 70 Super I/O Initialization
PEI_CPU_REG_INIT PEI 71 CPU Early Initialization
PEI_PCIE_MMIO_INIT PEI 74 PCIE MMIO BAR Initialization
PEI_NB_REG_INIT PEI 75 North Bridge Early Initialization
PEI_SB_REG_INIT PEI 76 South Bridge Early Initialization