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AU OPTRONICS CORPORATION
Product Specification
document version 1.0 18
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M240HW01 V2
Note1: Start from left side
Note2: Input signals of odd and even clock shall be the same timing.
6.4 Timing Characteristics
Basically, interface timing described here is not actual input timing of LCD module but close to
output timing of SN75LVDS82DGG (Texas Instruments) or equivalent.
Item Symbol Min Typ Max Unit
Data CLK
Tclk
40
75
90
[MHz]
Period Th 1034 1060 2047 [Tclk]
Display Area Tdisp(h) 960 960 960 [Tclk]
H-section
Blanking
Tblk(h)
74 100 1087 [Tclk]
Period Tv 1088 1120 2047 [Th]
Display Area Tdisp(v) 1080 1080 1080 [Th]
V-section
Blanking
Tblk(v)
8 40 967 [Th]
Frame Rate F 50 60 75 [Hz]
Note : DE mode only