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DIGITAL-LOGIC AG MSEBX800/900 Detailed Manual V1.0
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/Master, input
This signal is used with a DRQ line to gain control of the system. A processor or DMA controller on the
I/O channel may issue a DRQ to a DMA channel in cascade mode and receive a /DACK.
/MEMCS16, input
MEMCS16 Chip Select: signals the system board if the present data transfer is a 1 wait-state, 16bit,
memory cycle. It must be derived from the decode of LA17 through LA23. /MEMCS16 should be
driven with an open collector (300 Ohm pull-up) or tri-state driver capable of sinking 20mA.
/MEMR, input/output
These signals instruct the memory devices to drive data onto the data bus. /MEMR is active on all
memory read cycles. /MEMR may be driven by any microprocessor or DMA controller in the system.
When a microprocessor on the I/0 channel wishes to drive /MEMR, it must have the address lines
valid on the bus for one system clock period before driving /MEMR active. These signals are active
low.
/MEMW, input/output
These signals instruct the memory devices to store the data present on the data bus. /MEMW is active
in all memory read cycles. /MEMW may be driven by any microprocessor or DMA controller in the
system. When a microprocessor on the I/O channel wishes to drive /MEMW, it must have the address
lines valid on the bus for one system clock period before driving /MEMW active. Both signals are
active low.
OSC, output
Oscillator (OSC): a high-speed clock with a 70 nanosecond period (14.31818 MHz). This signal is not
synchronous with the system clock. It has a 50% duty cycle. OSC starts 100µs after reset is inactive.
RESETDRV, output
Reset Drive: used to reset or initiate system logic at power-up time or during a low line-voltage outage.
This signal is active high. When the signal is active all adapters should turn off or tri-state all drivers
connected to the I/O channel. This signal is driven by the permanent Master.
/REFRESH, input/output
These signals are used to indicate a refresh cycle and can be driven by a microprocessor on the I/O
channel. These signals are active low.
SA0-SA19, LA17 - LA23 input/output
Address bits 0 through 19 are used to address memory and I/0 devices within the system. These 20
address lines allow access of up to 1MByte of memory. SAO through SA19 are gated on the system
bus when BALE is high and are latched on the falling edge of BALE. LA17 to LA23 are not latched and
addresses the full 16MByte range. These signals are generated by the microprocessors or DMA
controllers. They may also be driven by other microprocessor or DMA controllers that reside on the I/0
channel. The SA17-SA23 are always LA17-LA23 address timings for use with the MSCS16 signal.
This is advanced AT96 design. The timing is selectable with jumpers LAxx or SAxx.
/SBHE, input/output
Bus High Enable (system): indicates a transfer of data on the upper byte of the data bus, XD8 through
XD15. Sixteen-bit devices use /SBHE to condition data-bus buffers tied to XD8 through XD15.
SD[0-15], input/output
These signals provide bus bits 0 through 15 for the microprocessor, memory, and I/O devices. D0 is
the least significant bit and D15 is the most significant bit. All 8bit devices on the I/O channel should
use D0 through D7 for communications to the microprocessor. The 16bit devices will use D0 through
D15. To support 8bit devices, the data on D8 through D15 will be gated to D0 through D7 during 8bit
transfers to these devices; 16bit microprocessor transfers to 8bit devices will be converted to two 8bit
transfers.
/SMEMR, input/output
These signals instruct the memory devices to drive data onto the data bus for the first MByte. /SMEMR
is active on all memory read cycles. /SMEMR may be driven by any microprocessor or DMA controller
in the system. When a microprocessor on the I/0 channel wishes to drive /SMEMR, it must have the
address lines valid on the bus for one system clock period before driving /SMEMR active. The signal is
active low.