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CY14B104L, CY14B104N
Document #: 001-07102 Rev. *L Page 12 of 25
AutoStore/Power Up RECALL
Parameters Description
CY14B104L/CY14B104N
Unit
Min Max
t
HRECALL
[20]
Power Up RECALL Duration 20 ms
t
STORE
[21]
STORE Cycle Duration 8 ms
t
DELAY
[22]
Time Allowed to Complete SRAM Cycle 1 70 μs
V
SWITCH
Low Voltage Trigger Level 2.65 V
t
VCCRISE
VCC Rise Time 150 μs
V
HDIS
[13]
HSB Output Driver Disable Voltage 1.9 V
t
HHHD
HSB High Active Time 500 ns
t
PURHH
HSB Hold Time after Power-Up Recall Start 70 μs
t
LZHSB
HSB To Output Active Time 5 μs
Switching Waveforms
Figure 11. AutoStore or Power Up RECALL
[23]
W
6725(
9
&&
9
6:,7&+
W
9&&5,6(
W
6725(
$XWR6WRUH
32:(583
5(&$//
W
+5(&$//
W
+5(&$//
5HDG:ULWH
,QKLELWHG
32:(583
5(&$//
5HDG:ULWH
%52:1287
$XWR6WRUH
32:(583
5(&$//
5HDG:ULWH
32:(5'2:1
$XWR6WRUH
1RWH
+6%
9
+',6
9
5(6(7
1RWH
W
'(/$<
W
'(/$<
W
/=+6%
W
/=+6%
287
W
385++
W
+++'
W
+++'
1RWH
Notes
20.t
HRECALL
starts from the time V
CC
rises above V
SWITCH.
21.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.
22.On a Hardware STORE, Software STORE/RECALL, AutoStore Enable/Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
DELAY
.
23.Read and Write cycles are ignored during STORE, RECALL, and while V
CC
is below V
SWITCH.
24.HSB pin is driven HIGH to V
CC
only by internal 100 kΩ resistor, HSB driver is disabled.
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