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CY14E102L, CY14E102N
Document Number: 001-45755 Rev. *A Page 11 of 21
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled
[12, 13, 23]
Figure 6. SRAM Read Cycle #2: CE and OE Controlled
[12, 23, 25]
t
RC
t
AA
t
OHA
ADDRESS
DQ (DATA OUT)
DATA VALID
ADDRESS
t
RC
CE
t
ACE
t
LZCE
t
PD
t
HZCE
OE
t
DOE
t
LZOE
DATA VALID
ACTIVE
STANDBY
t
PU
DQ (DATA OUT)
ICC
t
LZBE
t
DBE
t
HZBE
HZOE
t
t
HZCE
BHE , BLE
Notes
23.HSB
must remain HIGH during READ and WRITE cycles.
24.CE
or WE must be >V
IH
during address transitions.
25.BHE
and BLE are applicable for x16 configuration only.
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