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CY62138EV30
MoBL
®
Document #: 38-05577 Rev. *A Page 5 of 9
Switching Characteristics (Over the Operating Range)
[9]
Parameter Description
45 ns
UnitMin. Max.
Read Cycle
t
RC
Read Cycle Time 45 ns
t
AA
Address to Data Valid 45 ns
t
OHA
Data Hold from Address Change 10 ns
t
ACE
CE LOW to Data Valid 45 ns
t
DOE
OE LOW to Data Valid 22 ns
t
LZOE
OE LOW to Low Z
[10]
5ns
t
HZOE
OE HIGH to High Z
[10,11]
18 ns
t
LZCE
CE LOW to Low Z
[10]
10 ns
t
HZCE
CE HIGH to High Z
[10, 11]
18 ns
t
PU
CE LOW to Power-up 0 ns
t
PD
CE HIGH to Power-up 45 ns
Write Cycle
[12]
t
WC
Write Cycle Time 45 ns
t
SCE
CE LOW to Write End 35 ns
t
AW
Address Set-up to Write End 35 ns
t
HA
Address Hold from Write End 0 ns
t
SA
Address Set-up to Write Start 0 ns
t
PWE
WE Pulse Width 35 ns
t
SD
Data Set-up to Write End 25 ns
t
HD
Data Hold from Write End 0 ns
t
HZWE
WE LOW to High Z
[10, 11]
18 ns
t
LZWE
WE HIGH to Low Z
[10]
10 ns
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
Notes:
9. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2,
input pulse levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
10.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
11. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the output enter a high-impedance state.
12.The internal write time of the memory is defined by the overlap of WE
, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
13.Device is continuously selected. OE
, CE = V
IL
.
14.WE
is HIGH for read cycle.
ADDRESS
DATA OUT PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
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