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CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 16 of 19
Notes
49.t
HA
depends on which enable pin (CE
L
or R/W
L
) is deasserted first.
50.t
INS
or t
INR
depends on which enable pin (CE
L
or R/W
L
) is asserted last.
Switching Waveforms
(continued)
WRITE 1FFF (OR 1/3FFF)
t
WC
Right Side Clears INT
R
:
t
HA
READ 7FFF
t
RC
t
INR
WRITE 1FFE (OR 1/3FFE)
t
WC
Right SideSets INT
L
:
Left Side Sets INT
R
:
Left SideClears INT
L
:
READ 7FFE
t
INR
t
RC
ADDRESS
R
CE
L
R/W
L
INT
L
OE
L
ADDRESS
R
R/W
R
CE
R
INT
L
ADDRESS
R
CE
R
R/W
R
INT
R
OE
R
ADDRESS
L
R/W
L
CE
L
INT
R
t
INS
t
HA
t
INS
(OR 1/3FFF)
OR 1/3FFE)
[49]
[50]
[50]
[50]
[49]
[50]
Figure 16. Interrupt Timing Diagram
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