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CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document #: 38-06059 Rev. *S Page 13 of 28
Figure 6. AC Test Load and Waveforms
Switching Characteristics
Over the Operating Range
Parameter Description
-167 -133 -100
Unit
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0832BV
CY7C0833AV CY7C0833AV
Min Max Min Max Min Max Min Max
f
MAX2
Maximum Operating Frequency 167 133 133 100 MHz
t
CYC2
Clock Cycle Time 6.0 7.5 7.5 10 ns
t
CH2
Clock HIGH Time 2.7 3.0 3.0 4.0 ns
t
CL2
Clock LOW Time 2.7 3.0 3.0 4.0 ns
t
R
[27]
Clock Rise Time 2.0 2.0 2.0 3.0 ns
t
F
[27]
Clock Fall Time 2.0 2.0 2.0 3.0 ns
t
SA
Address Setup Time 2.3 2.5 2.5 3.0 ns
t
HA
Address Hold Time 0.6 0.6 0.6 0.6 ns
t
SB
Byte Select Setup Time 2.3 2.5 2.5 3.0 ns
t
HB
Byte Select Hold Time 0.6 0.6 0.6 0.6 ns
t
SC
Chip Enable Setup Time 2.3 2.5 NA NA ns
t
HC
Chip Enable Hold Time 0.6 0.6 NA NA ns
t
SW
R/W Setup Time 2.3 2.5 2.5 3.0 ns
t
HW
R/W Hold Time 0.6 0.6 0.6 0.6 ns
t
SD
Input Data Setup Time 2.3 2.5 2.5 3.0 ns
t
HD
Input Data Hold Time 0.6 0.6 0.6 0.6 ns
t
SAD
ADS Setup Time 2.3 2.5 NA NA ns
t
HAD
ADS Hold Time 0.6 0.6 NA NA ns
t
SCN
CNTEN Setup Time 2.3 2.5 NA NA ns
t
HCN
CNTEN Hold Time 0.6 0.6 NA NA ns
t
SRST
CNTRST Setup Time 2.3 2.5 NA NA ns
t
HRST
CNTRST Hold Time 0.6 0.6 NA NA ns
t
SCM
CNT/MSK Setup Time 2.3 2.5 NA NA ns
R1 = 590
Ω
R2 = 435
Ω
C = 5 pF
(b) Three-state Delay (Load 2)
90%
10%
3.0V
Vss
90%
10%
<
2ns < 2ns
ALL INPUT PULSES
3.3V
V
TH
= 1.5V
R = 50
Ω
Z
0
= 50
Ω
(a) Normal Load (Load 1)
C = 10 pF
OUTPUT
OUTPUT
Note
27.Except JTAG signals (t
r
and t
f
< 10 ns [max.]).
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