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Document #: 38-06059 Rev. *S Page 19 of 28
Figure 14. Write with Address Counter Advance
[39]
Figure 15. Counter Reset
[40, 41]
Switching Waveforms
(continued)
t
CH2
t
CL2
t
CYC2
A
n
A
n+1
A
n+2
A
n+3
A
n+4
D
n+1
D
n+1
D
n+2
D
n+3
D
n+4
A
n
D
n
t
SAD
t
HAD
t
SCN
t
HCN
t
SD
t
HD
WRITE EXTERNAL
WRITE WITH COUNTER
ADDRESS
WRITE WITH
COUNTER
WRITE COUNTER
HOLD
CLK
ADDRESS
INTERNAL
DATA
IN
ADDRESS
t
SA
t
HA
CNTEN
ADS
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATA
IN
ADDRESS
CNTRST
R/W
DATA
OUT
A
n
A
m
A
p
A
x
0
1
A
n
A
m
A
p
Q
1
Q
n
Q
0
D
0
t
CH2
t
CL2
t
CYC2
t
SA
t
HA
t
SW
t
HW
t
SRST
t
HRST
t
SD
t
HD
t
CD2
t
CD2
t
CKLZ
[42]
RESET ADDRESS 0
COUNTER WRITE READ
ADDRESS 0 ADDRESS 1
READ READ
ADDRESS A
n
ADDRESS A
m
READ
Notes
40.CE
0
= BE0 – BE1 = LOW; CE
1
= MRST = CNT/MSK = HIGH.
41.No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
42.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
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