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Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05477 Rev.*E Revised July 14, 2008
CY7C1062DV33
16 Mbit (512K X 32) Static RAM
Features
■ High speed
❐ t
AA
= 10 ns
■ Low active power
❐ I
CC
= 175 mA at 10 ns
■ Low CMOS standby power
❐ I
SB2
= 25 mA
■ Operating voltages of 3.3 ± 0.3V
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE
1
, CE
2
, and CE
3
features
■ Available in Pb-free 119-ball PBGA package
Functional Description
The CY7C1062DV33 is a high performance CMOS Static RAM
organized as 524,288 words by 32 bits.
To write to the device, take Chip Enables (CE
1,
CE
2,
and CE
3
LOW) and Write Enable (WE) input LOW. If Byte Enable A (B
A
)
is LOW, then data from IO pins (IO
0
through IO
7
) is written into
the location specified on the address pins (A
0
through A
18
). If
Byte Enable B (B
B
) is LOW, then data from IO pins (IO
8
through
IO
15
) is written into the location specified on the address pins (A
0
through A
18
). Likewise, B
C
and B
D
correspond with the IO pins
IO
16
to IO
23
and IO
24
to IO
31
, respectively.
To read from the device, take Chip Enables (CE
1,
CE
2
,
and CE
3
LOW) and Output Enable (OE) LOW while forcing the Write
Enable (WE
) HIGH. If the first B
A
is LOW, then data from the
memory location specified by the address pins appear on IO
0
to
IO
7
. If B
B
is LOW, then data from memory appears on IO
8
to IO
15
.
Likewise, B
c
and B
D
correspond to the third and fourth bytes.
See Truth Table on page 9 for a complete description of read and
write modes.
The input and output pins (IO
0
through IO
31
) are placed in a high
impedance state when the device is deselected (CE
1,
CE
2,
or
CE
3
HIGH), the outputs are disabled (OE HIGH), the byte selects
are disabled (B
A-D
HIGH), or during a write operation (CE
1,
CE
2
and CE
3
LOW and WE LOW).
Logic Block Diagram
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFERS
512K x 32
ARRAY
IO
0
– IO
31
OE
CE
3
B
A
B
D
OUTPUT BUFFERS
CONTROL LOGIC
B
B
B
C
WE
CE
2
CE
1
A
(9:0)
A
(18:10)
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