CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Document Number: 001-06582 Rev. *D Page 24 of 29
DLL Timing
t
KC Var
t
KC Var
Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 ns
t
KC lock
t
KC lock
DLL Lock Time (K) 2048 – 2048 – 2048 – 2048 – Cycles
t
KC Reset
t
KC Reset
K Static to DLL Reset
[30]
30–30–30–30– ns
Switching Characteristics
Over the operating range
[23, 24]
(continued)
Cypress
Parameter
Consortium
Parameter
Description
400 MHz 375 MHz 333 MHz 300 MHz
Unit
Min Max Min Max Min Max Min Max
Note
30.Hold to >V
IH
or <V
IL
.
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