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CY7C1324H
Document #: 001-00208 Rev. *B Page 11 of 15
Write Cycle Timing
[15, 16]
Note:
16.
Full width Write can be initiated by either GW
LOW; or by GW HIGH, BWE LOW and BW
[A:B]
LOW.
Timing Diagrams (continued)
t
CYC
t
CL
CLK
t
ADH
t
ADS
ADDRESS
t
CH
t
AH
t
AS
A1
t
CEH
t
CES
High-Z
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A2 + 1)
D(A1)
D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)
A2 A3
Extended BURST WRITE
D(A2 + 2)
Single WRITE
t
ADH
t
ADS
t
ADH
t
ADS
t
OEHZ
t
ADVH
t
ADVS
t
WEH
t
WES
t
DH
t
DS
t
WEH
t
WES
Byte write signals are ignored for first cycle when
ADSP initiates burst.
ADSC extends burst.
ADV suspends burst.
DON’T CARE UNDEFINED
ADSP
ADSC
BWE,
BW
[A:B]
GW
CE
ADV
OE
Data in (D)
D
ata Out (Q)
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