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CY7C1370DV25
CY7C1372DV25
Document #: 38-05558 Rev. *D Page 21 of 27
Notes:
27.The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN
being used to create a pause. A write is not performed during this cycle
28.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29.I/Os are in High-Z when exiting ZZ sleep mode.
NOP,STALL and DESELECT Cycles
[24, 25, 27]
ZZ Mode Timing
[28, 29]
Switching Waveforms (continued)
READ
Q(A3)
45678910
CLK
CE
WE
CEN
BWx
ADV/LD
ADDRESS
A3 A4
A5
D(A4)
Data
In-Out (DQ)
A1
Q(A5)
WRITE
D(A4)
STALLWRITE
D(A1)
123
READ
Q(A2)
STALL NOP READ
Q(A5)
DESELECT CONTINUE
DESELECT
DON’T CARE UNDEFINED
t
CHZ
A2
D(A1) Q(A2) Q(A3)
t
ZZ
I
SUPPLY
CLK
ZZ
t
ZZREC
A
LL INPUTS
(except ZZ)
DON’T CARE
I
DDZZ
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
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