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CY7C145, CY7C144
Document #: 38-06034 Rev. *D Page 10 of 21
Figure 10. Semaphore Read After Write Timing, Either Side
[25]
Figure 11. Semaphore Contention
[26, 27, 28]
Notes
25.CE
= HIGH for the duration of the above timing (both write and read cycle).
26.I/O
0R
= I/O
0L
= LOW (request semaphore); CE
R
= CE
L
= HIGH
27.Semaphores are reset (available to both ports) at cycle start.
28.If t
SPS
is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
Switching Waveforms (continued)
t
SOP
t
AA
SEM
R/W
OE
I/O
0
VALID ADDRESS VALID ADDRESS
t
HD
DATA
IN
VALID
DATA
OUT
VALID
t
OHA
A
0
−A
2
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE READ CYCLE
MATCH
t
SPS
A
0L
−A
2L
MATCH
R/W
L
SEM
L
A
0R
−A
2R
R/W
R
SEM
R
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