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CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Document #: 001-15031 Rev. *C Page 22 of 30
Switching Characteristics
Over the Operating Range. Timing reference is 1.5V when V
DDQ
= 3.3V and is 1.25V when V
DDQ
= 2.5V. Test conditions shown in
(a) of “AC Test Loads and Waveforms” on page 21 unless otherwise noted.
Parameter Description
–250 –200 –167
Unit
Min Max Min Max Min Max
t
Power
[16]
V
CC
(typical) to the First Access Read or Write 1 1 1 ms
Clock
t
CYC
Clock Cycle Time 4.0 5.0 6.0 ns
F
MAX
Maximum Operating Frequency 250 200 167 MHz
t
CH
Clock HIGH 2.0 2.0 2.2 ns
t
CL
Clock LOW 2.0 2.0 2.2 ns
Output Times
t
CO
Data Output Valid After CLK Rise 3.0 3.0 3.4 ns
t
OEV
OE LOW to Output Valid 3.0 3.0 3.4 ns
t
DOH
Data Output Hold After CLK Rise 1.3 1.3 1.5 ns
t
CHZ
Clock to High-Z
[17, 18, 19]
3.0 3.0 3.4 ns
t
CLZ
Clock to Low-Z
[17, 18, 19]
1.3 1.3 1.5 ns
t
EOHZ
OE HIGH to Output High-Z
[17, 18, 19]
3.0 3.0 3.4 ns
t
EOLZ
OE LOW to Output Low-Z
[17, 18, 19]
0 0 0 ns
Setup Times
t
AS
Address Setup Before CLK Rise 1.4 1.4 1.5 ns
t
DS
Data Input Setup Before CLK Rise 1.4 1.4 1.5 ns
t
CENS
CEN Setup Before CLK Rise 1.4 1.4 1.5 ns
t
WES
WE, BW
x
Setup Before CLK Rise 1.4 1.4 1.5 ns
t
ALS
ADV/LD Setup Before CLK Rise 1.4 1.4 1.5 ns
t
CES
Chip Select Setup 1.4 1.4 1.5 ns
Hold Times
t
AH
Address Hold After CLK Rise 0.4 0.4 0.5 ns
t
DH
Data Input Hold After CLK Rise 0.4 0.4 0.5 ns
t
CENH
CEN Hold After CLK Rise 0.4 0.4 0.5 ns
t
WEH
WE, BW
x
Hold After CLK Rise 0.4 0.4 0.5 ns
t
ALH
ADV/LD Hold after CLK Rise 0.4 0.4 0.5 ns
t
CEH
Chip Select Hold After CLK Rise 0.4 0.4 0.5 ns
Notes
16.This part has an internal voltage regulator; t
power
is the time power is supplied above V
DD
minimum initially, before a read or write operation can be initiated.
17.t
CHZ
, t
CLZ
, t
EOLZ
, and t
EOHZ
are specified with AC test conditions shown in (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ±200 mV
from steady-state voltage.
18.At any voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z before Low-Z under the same system conditions.
19.This parameter is sampled and not 100% tested.
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