Cypress CY7C1482V25 Computer Hardware User Manual


 
CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *H Page 19 of 32
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DD
Relative to GND........ –0.3V to +3.6V
Supply Voltage on V
DDQ
Relative to GND ......–0.3V to +V
DD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage ...................................–0.5V to V
DD
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch Up Current .................................................... >200 mA
Operating Range
Range
Ambient
Temperature
V
DD
V
DDQ
Commercial 0°C to +70°C 2.5V –5%/+5% 1.7V to
V
DD
Industrial –40°C to +85°C
Electrical Characteristics Over the Operating Range
[12, 13]
Parameter Description Test Conditions Min Max Unit
V
DD
Power Supply Voltage 2.375 2.625 V
V
DDQ
IO Supply Voltage for 2.5V IO 2.375 V
DD
V
for 1.8V IO 1.7 1.9 V
V
OH
Output HIGH Voltage for 2.5V IO, I
OH
= –1.0 mA 2.0 V
for 1.8V IO, I
OH
= –100 µA1.6V
V
OL
Output LOW Voltage for 2.5V IO, I
OL
= 1.0 mA 0.4 V
for 1.8V IO, I
OL
= 100 µA0.2V
V
IH
Input HIGH Voltage
[12]
for 2.5V IO 1.7 V
DD
+ 0.3V V
for 1.8V IO 1.26 V
DD
+ 0.3V V
V
IL
Input LOW Voltage
[12]
for 2.5V IO –0.3 0.7 V
for 1.8V IO –0.3 0.36 V
I
X
Input Leakage Current
except ZZ and MODE
GND V
I
V
DDQ
–5 5 µA
Input Current of MODE Input = V
SS
–30 µA
Input = V
DD
5 µA
Input Current of ZZ Input = V
SS
–5 µA
Input = V
DD
30 µA
I
OZ
Output Leakage Current GND V
I
V
DDQ,
Output Disabled –5 5 µA
I
DD
V
DD
Operating Supply
Current
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
4.0-ns cycle, 250 MHz 450 mA
5.0-ns cycle, 200 MHz 450 mA
6.0-ns cycle, 167 MHz 400 mA
I
SB1
Automatic CE
Power Down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
f = f
MAX
= 1/t
CYC
4.0-ns cycle, 250 MHz 200 mA
5.0-ns cycle, 200 MHz 200 mA
6.0-ns cycle, 167 MHz 200 mA
I
SB2
Automatic CE
Power Down
Current—CMOS Inputs
V
DD
= Max, Device Deselected,
V
IN
0.3V or V
IN
> V
DDQ
– 0.3V,
f = 0
All speeds 120 mA
I
SB3
Automatic CE
Power Down
Current—CMOS Inputs
V
DD
= Max, Device Deselected, or
V
IN
0.3V or V
IN
> V
DDQ
– 0.3V
f = f
MAX
= 1/t
CYC
4.0-ns cycle, 250 MHz 200 mA
5.0-ns cycle, 200 MHz 200 mA
6.0-ns cycle, 167 MHz 200 mA
I
SB4
Automatic CE
Power Down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
, f = 0
All speeds 135 mA
Notes
12. Overshoot: V
IH
(AC) < V
DD
+1.5V (Pulse width less than t
CYC
/2), undershoot: V
IL
(AC) > –2V (Pulse width less than t
CYC
/2).
13.Power up: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
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