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CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *H Page 24 of 32
Read/Write Cycle Timing
[21, 23, 24]
Switching Waveforms (continued)
t
CYC
t
CL
CLK
ADSP
t
ADH
t
ADS
ADDRESS
t
CH
OE
ADSC
CE
t
AH
t
AS
A2
t
CEH
t
CES
D
ata Out (Q)
High-Z
ADV
Single WRITE
D(A3)
A4 A5 A6
D(A5) D(A6)
Data In (D)
BURST READBack-to-Back READs
High-Z
Q(A2)Q(A1)
Q(A4) Q(A4+1) Q(A4+2)
t
WEH
t
WES
Q(A4+3)
t
OEHZ
t
DH
t
DS
t
OELZ
t
CLZ
t
CO
Back-to-Back
WRITEs
A1
DON’T CARE UNDEFINED
A3
BWE,
BW
X
Notes
23.The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP
or ADSC.
24.GW
is HIGH.
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