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CY7C1392BV18, CY7C1992BV18
CY7C1393BV18, CY7C1394BV18
Document #: 38-05623 Rev. *D Page 2 of 31
Logic Block Diagram (CY7C1392BV18)
Logic Block Diagram (CY7C1992BV18)
1M x 8 Array
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Read Add. Decode
Read Data Reg.
LD
Q
[7:0]
Reg.
Reg.
Reg.
8
8
16
8
NWS
[1:0]
V
REF
Write Add. Decode
Write
Data Reg
8
8
20
8
R/W
LD
R/W
CQ
CQ
DOFF
1M x 8 Array
Write
Data Reg
Control
Logic
C
C
1M x 9 Array
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
Read Add. Decode
Read Data Reg.
LD
Q
[8:0]
Reg.
Reg.
Reg.
9
18
9
BWS
[0]
V
REF
Write Add. Decode
Write
Data Reg
9
9
20
9
R/W
LD
R/W
CQ
CQ
DOFF
1M x 9 Array
Write
Data Reg
Control
Logic
C
C
9
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