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CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 29 of 62
5. Register Summary
FX2LP register bit definitions are described in the FX2LP TRM in greater detail.
Table 12. FX2LP Register Summary
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
GPIF Waveform Memories
E400 128 WAVEDATA GPIF Waveform
Descriptor 0, 1, 2, 3 data
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E480 128 reserved
GENERAL CONFIGURATION
E50D GPCR2 General Purpose Configu-
ration Register 2
reserved reserved reserved FULL_SPEE
D_ONLY
reserved reserved reserved reserved 00000000 R
E600 1 CPUCS CPU Control & Status 0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 8051RES 00000010 rrbbbbbr
E601 1 IFCONFIG Interface Configuration
(Ports, GPIF, slave FIFOs)
IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0 10000000 RW
E602 1 PINFLAGSAB
[11]
Slave FIFO FLAGA and
FLAGB Pin Configuration
FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 00000000 RW
E603 1 PINFLAGSCD
[11]
Slave FIFO FLAGC and
FLAGD Pin Configuration
FLAGD3 FLAGD2 FLAGD1 FLAGD0 FLAGC3 FLAGC2 FLAGC1 FLAGC0 00000000 RW
E604 1 FIFORESET
[11]
Restore FIFOS to default
state
NAKALL 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
E605 1 BREAKPT Breakpoint Control 0 0 0 0 BREAK BPPULSE BPEN 0 00000000 rrrrbbbr
E606 1 BPADDRH Breakpoint Address H A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW
E607 1 BPADDRL Breakpoint Address L A7 A6 A5 A4 A3 A2 A1 A0 xxxxxxxx RW
E608 1 UART230 230 Kbaud internally
generated ref. clock
0 0 0 0 0 0 230UART1 230UART0 00000000 rrrrrrbb
E609 1 FIFOPINPOLAR
[11]
Slave FIFO Interface pins
polarity
0 0 PKTEND SLOE SLRD SLWR EF FF 00000000 rrbbbbbb
E60A 1 REVID Chip Revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 RevA
00000001
R
E60B 1 REVCTL
[11]
Chip Revision Control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb
UDMA
E60C 1 GPIFHOLDAMOUNT MSTB Hold Time
(for UDMA)
0 0 0 0 0 0 HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
3 reserved
ENDPOINT CONFIGURATION
E610 1 EP1OUTCFG Endpoint 1-OUT
Configuration
VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
E611 1 EP1INCFG Endpoint 1-IN
Configuration
VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
E612 1 EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 10100010 bbbbbrbb
E613 1 EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 10100000 bbbbrrrr
E614 1 EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 11100010 bbbbbrbb
E615 1 EP8CFG Endpoint 8 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 11100000 bbbbrrrr
2 reserved
E618 1 EP2FIFOCFG
[11]
Endpoint 2 / slave FIFO
configuration
0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
E619 1 EP4FIFOCFG
[11]
Endpoint 4 / slave FIFO
configuration
0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
E61A 1 EP6FIFOCFG
[11]
Endpoint 6 / slave FIFO
configuration
0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
E61B 1 EP8FIFOCFG
[11]
Endpoint 8 / slave FIFO
configuration
0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
E61C 4 reserved
E620 1 EP2AUTOINLENH
[11
Endpoint 2 AUTOIN
Packet Length H
0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
E621 1 EP2AUTOINLENL
[11]
Endpoint 2 AUTOIN
Packet Length L
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E622 1 EP4AUTOINLENH
[11]
Endpoint 4 AUTOIN
Packet Length H
0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
E623 1 EP4AUTOINLENL
[11]
Endpoint 4 AUTOIN
Packet Length L
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E624 1 EP6AUTOINLENH
[11]
Endpoint 6 AUTOIN
Packet Length H
0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
E625 1 EP6AUTOINLENL
[11]
Endpoint 6 AUTOIN
Packet Length L
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E626 1 EP8AUTOINLENH
[11]
Endpoint 8 AUTOIN
Packet Length H
0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
E627 1 EP8AUTOINLENL
[11]
Endpoint 8 AUTOIN
Packet Length L
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E628 1 ECCCFG ECC Configuration 0 0 0 0 0 0 0 ECCM 00000000 rrrrrrrb
E629 1 ECCRESET ECC Reset x x x x x x x x 00000000 W
E62A 1 ECC1B0 ECC1 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R
Note
11. Read and writes to these registers may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
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