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CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Document 001-05809 Rev. *A Page 22 of 42
Table 11.Configuration Data Organization
Byte
Address
Configuration
Item Name
Configuration
Item Description
Required
Contents
Variable
Contents
Note Devices running in Backward Compatibility (CY7C68300A) Mode must use the CY7C68300A EEPROM organization, and
not the format shown in this document. Refer to the CY7C68300A data sheet for the CY7C68300A EEPROM format.
AT2LP Configuration
0x00 EEPROM signature byte 0 I
2
C EEPROM signature byte 0. This byte must be 0x53 for
proper AT2LP pin configuration.
0x53
0x01 EEPROM signature byte 1 I
2
C EEPROM signature byte 1. This byte must be 0x4B for
proper AT2LP pin configuration.
0x4B
0x02 APM Value ATA Device Automatic Power Management Value. If an
attached ATA device supports APM and this field contains
other than 0x00, the AT2LP issues a SET_FEATURES
command to Enable APM with this value during the drive
initialization process. Setting APM Value to 0x00 disables
this functionality. This value is ignored with ATAPI devices.
0x00
0x03 Reserved Must be set to 0x00. 0x00
0x04 bVSCBSignature Value Value in the first byte of the CBW CB field that designates
that the CB is to be decoded as vendor specific ATA
commands instead of the ATAPI command block. See
“Functional Overview” on page 15 for more detail on how
this byte is used.
0x24
0x05 Reserved Bits 7:6 0x07
Enable mode page 8 Bit 5
Enable the write caching mode page (page 8). If this page
is enabled, Windows disables write caching by default,
which limits write performance.
0= Disable mode page 8.
1= Enable mode page 8.
Disable wait for INTRQ Bit 4
Poll status register rather than waiting for INTRQ. Setting
this bit to 1 improves USB BOT test results but may
introduce compatibility problems with some devices.
0 = Wait for INTRQ.
1 = Poll status register instead of using INTRQ.
BUSY Bit Delay Bit 3
Enable a delay of up to 120 ms at each read of the DRQ bit
where the device data length does not match the host data
length. This allows the CY7C68300C/CY7C68301C to work
with most devices that incorrectly clear the BUSY bit before
a valid status is present.
0 = No BUSY bit delay.
1 = Use BUSY bit delay.
Short Packet Before Stall Bit 2
Determines if a short packet is sent before the STALL of an
IN endpoint. The USB Mass Storage Class Bulk-Only Speci-
fication allows a device to send a short or zero-length IN
packet before returning a STALL handshake for certain
cases. Certain host controller drivers may require a short
packet before STALL.
0 = Do not force a short packet before STALL.
1 = Force a short packet before STALL.
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