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CY8C23433, CY8C23533
Document Number: 001-44369 Rev. *B Page 32 of 37
AC External Clock Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
AC Programming Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
SAR8 ADC AC Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 32. 5V AC External Clock Specifications
Symbol Description Min Typ Max Units
F
OSCEXT
Frequency 0.093 – 24.6 MHz
– High Period 20.6
– 5300 ns
– Low Period 20.6 – –ns
– Power Up IMO to Switch 150
– – μs
Table 33. 3.3V AC External Clock Specifications
Symbol Description Min Typ Max Units
F
OSCEXT
Frequency with CPU Clock divide by 1
[18]
0.093 – 12.3 MHz
F
OSCEXT
Frequency with CPU Clock divide by 2 or greater
[19]
0.186 – 24.6 MHz
– High Period with CPU Clock divide by 1 41.7 – 5300 ns
– Low Period with CPU Clock divide by 1 41.7
– –ns
– Power Up IMO to Switch 150 – – μs
Notes
18. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
19.If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
20.The max sample rate in this R2R ADC is 3.0/8=375KSPS
Table 34. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
T
RSCLK
Rise Time of SCLK 1 – 20 ns
T
FSCLK
Fall Time of SCLK 1 – 20 ns
T
SSCLK
Data Set up Time to Falling Edge of SCLK 40 – – ns
T
HSCLK
Data Hold Time from Falling Edge of SCLK 40 – – ns
F
SCLK
Frequency of SCLK 0 – 8 MHz
T
ERASEB
Flash Erase Time (Block) – 20 – ms
T
WRITE
Flash Block Write Time – 20 – ms
T
DSCLK
Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6
T
DSCLK3
Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6
Table 35. SAR8 ADC AC Specifications
[20]
Symbol Description Min Typ Max Units
Freq
3
Input clock frequency 3V – –3.075MHz
Freq
5
Input clock frequency 5V – –3.075MHz
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