Cypress CYD04S36V Computer Hardware User Manual


 
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Document Number: 38-06076 Rev. *G Page 14 of 28
t
HCM
CNT/MSK Hold Time 0.6 0.6 NA NA ns
t
OE
Output Enable to Data Valid 4.4 4.4 5.5 5.5 ns
t
OLZ
[31, 32]
OE to Low Z 0 0 0 0 ns
t
OHZ
[31, 32]
OE to High Z 0 4.0 0 4.4 0 5.5 0 5.5 ns
t
CD2
Clock to Data Valid 4.4 4.4 5.0 5.2 ns
t
CA2
Clock to Counter Address Valid 4.0 4.4 NA NA ns
t
CM2
Clock to Mask Register Readback
Valid
4.0 4.4 NA NA ns
t
DC
Data Output Hold After Clock HIGH 1.0 1.0 1.0 1.0 ns
t
CKHZ
[31, 32]
Clock HIGH to Output High Z 0 4.0 0 4.4 0 4.7 0 5.0 ns
t
CKLZ
[31, 32]
Clock HIGH to Output Low Z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns
t
SINT
Clock to INT Set Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10.0 ns
t
RINT
Clock to INT Reset Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10.0 ns
t
SCINT
Clock to CNTINT Set Time 0.5 5.0 0.5 5.7 NA NA NA NA ns
t
RCINT
Clock to CNTINT Reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns
Port to Port Delays
t
CCS
Clock to Clock Skew 5.2 6.0 5.7 8.0 ns
Master Reset Timing
t
RS
Master Reset Pulse Width 5.0 5.0 5.0 5.0 cycles
t
RS
Master Reset Setup Time 6.0 6.0 6.0 8.5 ns
t
RSR
Master Reset Recovery Time 5.0 5.0 5.0 5.0 cycles
t
RSF
Master Reset to Outputs Inactive 10.0 10.0 10.0 10.0 ns
t
RSINT
Master Reset to Counter and Mailbox
Interrupt Flag Reset Time
10.0 10.0 NA NA ns
Switching Characteristics Over the Operating Range (continued)
Parameter Description
-167 -133 -100
Unit
CYD01S36V
CYD02S36V/
CYD02S36VA
CYD04S36V
CYD09S36V
CYD01S36V
CYD02S36V
CYD04S36V
CYD09S36V
CYD18S36V CYD18S36V
Min Max Min Max Min Max Min Max
Notes
31.This parameter is guaranteed by design, but it is not production tested.
32.Test conditions used are Load 2.
JTAG Timing
Parameter Description
167/133/100
Unit
Min Max
f
JTAG
Maximum JTAG TAP Controller Frequency 10 MHz
t
TCYC
TCK Clock Cycle Time 100 ns
t
TH
TCK Clock HIGH Time 40 ns
t
TL
TCK Clock LOW Time 40 ns
t
TMSS
TMS Setup to TCK Clock Rise 10 ns
t
TMSH
TMS Hold After TCK Clock Rise 10 ns
t
TDIS
TDI Setup to TCK Clock Rise 10 ns
t
TDIH
TDI Hold After TCK Clock Rise 10 ns
t
TDOV
TCK Clock LOW to TDO Valid 30 ns
t
TDOX
TCK Clock LOW to TDO Invalid 0 ns
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