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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Document Number: 38-06076 Rev. *G Page 17 of 28
Figure 9. Bank Select Read
[37, 38]
Figure 10. Read-to-Write-to-Read (OE = LOW)
[36, 39, 40, 41, 42]
Notes
37.In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx36 device from this data sheet. ADDRESS
(B1)
= ADDRESS
(B2)
.
38. ADS
= CNTEN= BE0 – BE3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
39.Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
40.During “No Operation,” data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.
41. CE
0
= OE = BE0 – BE3 = LOW; CE
1
= R/W = CNTRST = MRST = HIGH.
42.CE
0
= BE0 – BE3 = R/W = LOW; CE
1
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed
(labelled as no operation). One clock cycle is required to three-state the IO for the Write operation on the next rising edge of CLK.
Switching Waveforms (continued)
Q
3
Q
1
Q
0
Q
2
A
0
A
1
A
2
A
3
A
4
A
5
Q
4
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
t
SC
t
HC
t
SA
t
HA
t
SC
t
HC
t
SC
t
HC
t
SC
t
HC
t
CKHZ
t
DC
t
DC
t
CD2
t
CKLZ
t
CD2
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CH2
t
CL2
t
CYC2
CLK
ADDRESS
(B1)
CE
(B1)
DATA
OUT(B2)
DATA
OUT(B1)
ADDRESS
(B2)
CE
(B2)
t
CYC2
t
CL2
t
CH2
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
t
HW
t
SW
t
CD2
t
DC
t
SD
t
HD
WRITE
CLK
CE
R/W
ADDRESS
DATA
IN
DATA
OUT
A
n
A
n+1
A
n+2
A
n+2
D
n+2
A
n+2
A
n+3
Q
n
t
CKHZ
NO OPERATION
READ
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