Filter
Top Products
February 19, 2008 Document No. 001-15342 Rev. ** 18
AN6077
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x82; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x84; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x86; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x88; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;
PINFLAGSAB = 0xEF; // FLAGA - fixed EP8FF, FLAGB - fixed EP6FF
SYNCDELAY;
PINFLAGSCD = 0x98; // FLAGC - fixed EP2EF, FLAGD - fixed EP4EF
SYNCDELAY;
PORTACFG |= 0x80; // FLAGD, set alt. func. of PA7 pin
SYNCDELAY;
FIFOPINPOLAR = 0x00; // all signals active low
SYNCDELAY;
EP2CFG = 0xA0;
SYNCDELAY;
EP6CFG = 0xE0;
// EP4 and EP8 are not used in this implementation
SYNCDELAY; //
EP4CFG = 0x20; // clear valid bit
SYNCDELAY; //
EP8CFG = 0x60; // clear valid bit
// handle the case where we were already in AUTO mode
EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0
SYNCDELAY;
SYNCDELAY; //
EP2BCL = 0x00; // arm first buffer
SYNCDELAY; //
EP2BCL = 0x00; // arm second buffer
SYNCDELAY; //
EP2BCL = 0x00; // arm third buffer
SYNCDELAY; //
EP2BCL = 0x00; // arm fourth buffer
SYNCDELAY; //
SYNCDELAY;
OUTPKTEND = 0x02;
SYNCDELAY;
OUTPKTEND = 0x02;
SYNCDELAY;
OUTPKTEND = 0x02;
SYNCDELAY;
OUTPKTEND = 0x02;
SYNCDELAY;
[+] Feedback