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February 19, 2008 Document No. 001-15342 Rev. ** 2
AN6077
GPIF Master Pin Descriptions
The GPIF pin names, descriptions, and their uses are dis-
cussed in this section.
RDYn Inputs
RDY[5:0] are ‘ready’ inputs that can be sampled and allow a
transaction to wait (inserting wait states), continue, or repeat
until the signal is at the appropriate level. This implementa-
tion uses RDY0 and RDY1 to control data flow.
RDY0 is tied to FLAGC (EP2 Empty Flag) of the slave and
RDY1 is tied to FLAGB (EP6 Full Flag) of the slave.
Other RDY inputs may be used in the application for addi-
tional debug status information.
CTLx Outputs
CTL[5:0] are programmable control outputs that are used as
strobes, read/write lines, or other outputs.
CTL0, CTL1 and CTL2 are used in this application.
CTL0 is tied to SLRD of the slave.
CTL1 is tied to SLWR of the slave.
CTL2 is tied to PKTEND of the slave.
FD[0:7]
This implementation has an 8-bit data bus. PORTB[0:7]
serves as the data bus on both the master and the slave.
PORTA[6:7]
PA6 and PA7 are tied to FIFOADR0 and FIFOADR1 of the
slave. These are used to drive the address of the FIFO being
accessed by the master.
Slave FIFO Pin Descriptions
The slave FIFO pin names, descriptions, and their uses are
discussed in this section.
SLRD
SLRD is the Slave Read line for the FIFO. SLRD acts as the
read strobe for the slave. CTL0 of the master provides the
strobe.
SLWR
SLWR is the Slave Write line for the FIFO. SLWR acts as the
write strobe for the slave. CTL1 of the master provides the
strobe.
SLOE
In this implementation SLOE is tied to SLRD.
FD[0:7]
This is Port B, which is configured as the 8-bit data bus. If the
WORDWIDE bit of the IFCONFIG register is set, then port D
is configured to be FD[8:15]. This implementation has an 8-bit
interface.
FLAGA/FLAGB/FLAGC/FLAGD
FLAGC is used to indicate the state of ‘emptiness’ of the end-
point 2 FIFO of the slave. FLAGB is used to indicate the state
of ‘fullness’ of the endpoint 6 FIFO of the slave.
FLAGA and FLAGD are not used in this implementation.
FIFOADR[0:1]
The master selects one of the four slave FIFOs using the
FIFOADR pins, and then drives the 8-bit FIFO data using the
SLRD (Slave Read) and SLWR (Slave Write) signals.
PKTEND
PKTEND is used to dispatch a short (less than the maximum
packet size) IN packet to the USB. In this implementation, it is
tied to CTL2 of the master EZ-USB FX2LP.
Creating GPIF Waveforms
This section describes the parameters to create a waveform
and includes figures for graphical clarity. Example code is
also included.
FIFORD
When creating the FIFORD waveform the following timing
parameters must be met.
tRD
pwl
- SLRD Pulse Width LOW = 50 ns (minimum)
tRD
pwh
- SLRD Pulse Width HIGH = 50 ns (minimum)
tXFLG - SLRD to FLAGS Output Propagation Delay =
70 ns (maximum)
tXFD - SLRD to FIFO Data Output Propagation Delay =
15 ns (maximum)
tOE
on
- SLOE Turn on to FIFO Data Valid = 10.5 ns (maxi-
mum)
tOE
off
- SLOE Turn off to FIFO Data Hold = 10.5 ns (maxi-
mum)
This results in the following sequence:
s0 Sample the empty flag of the peripheral. If the periph-
eral is ‘not empty’, proceed to s1 else go to s6 where
an interrupt is triggered and the waveform is aborted.
s1 Assert the SLRD strobe and wait for three cycles to
meet the tRD
pwl
parameter.
s2 Sample the data bus.
s3 Branch to IDLE.
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