![](http://pdfasset.owneriq.net/8/03/803650e2-9bc1-438e-a7ca-4ea1a17069dd/803650e2-9bc1-438e-a7ca-4ea1a17069dd-bg2a.png)
NOTE: DIMMs in sockets A1 to A6 are assigned to processor 1 and DIMMs in sockets B1 to B6 are assigned to
processor 2.
Figure 16. Memory Socket Locations
Memory channels are organized as follows:
Processor 1 channel 1: memory sockets A1 and A4
channel 2: memory sockets A2 and A5
channel 3: memory sockets A3 and A6
Processor 2 channel 1: memory sockets B1 and B4
channel 2: memory sockets B2 and B5
channel 3: memory sockets B3 and B6
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