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VXI Programming Using the IEEE 1394 Serial Bus 43Chapter 3
HP E8491A
Triggering
The HP E8491A is capable of asserting, receiving, and routing trigger
signals along the VXI (mainframe) backplane trigger lines. In addition to the
VXI backplane’s eight TTL level trigger lines and two ECL level trigger
lines, the E8491A can receive and assert triggers on the faceplate ‘Trig In’
and ‘Trig Out’ connectors.
Table 3-1 summarizes the triggering parameters and capabilities of the
HP E8491A.
Using Triggers The triggering functionality of the HP E8491A is accessed through the
following HP VISA and SICL functions:
Asserting Triggers - HP VISA
viSetAttribute
VI_ATTR_TRIG_ID
VI_TRIG_TTL0 to VI_TRIG_TTL7
VI_TRIG_ECL0 to VI_TRIG_ECL1
viAssertTrigger
VI_TRIG_PROT_DEFAULT
Table 3-1. HP E8491A Triggering Parameters.
Trigger Lines Trigger Levels Trigger Routing
TTLTRG7 - TTLTRG0
(VXI backplane)
Trigger levels or pulses can be
output on any number of
TTLTRG trigger lines.
One TTLTRG trigger line can be
routed to one ECLTRG trigger line.
ECLTRG1 - ECLTRG0
(VXI backplane)
Trigger levels or pulses can be
output on any number of
ECLTRG trigger lines.
One ECLTRG trigger line can be
routed to one TTLTRG trigger line.
Trig In Port*
(HP E8491A faceplate)
Input trigger levels are TTL, ECL,
CMOS, or programmable up to
+30V. Default assumes TTL low
true signal.
Input triggers can be routed to any
number of TTLTRG trigger lines and
to any number of ECLTRG trigger
lines.
Trig Out Port*
(HP E8491A faceplate)
Output trigger level is +5V (low
true - default) and can be pulled
to +30V.
One TTLTRG or ECLTRG trigger line
can be routed to the Trig Out port
* The E8491A Trig In and Trig Out ports are configured using the HP I_O Libraries ‘I_O Config’
utility.