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System architecture
HP Integrity midrange servers are built around a modular architecture, with components that can be
configured to effectively cover a wide range of computing needs. Both the Integrity rx7620-16 and
8620-32 Servers support a variety of system configurations, ranging from two to eight 1.6 or 1.5
GHz Intel Itanium 2 processors or from two to 16 1.1 GHz Intel Itanium 2 processors, using HP mx2
Dual-Processor Modules. Both servers can be configured as large symmetric multiprocessing (SMP)
systems or as multiple independent hard partitions (nPars). The basic components in the HP Integrity
midrange servers are the cell board, the PCI-X–based I/O subsystem, and, in the Integrity rx8620-32
Server, the crossbar backplane. These components fit together to provide a high-performance,
scalable, highly available, and flexible computing platform.
The HP mx2 Dual-Processor Module allows the Integrity rx7620-16 and rx8620-32 Servers’ chassis
to be expanded to allow 16 processors and 32 processors, respectively, in the existing chassis. The
HP mx2 Dual-Processor Module consists of two Intel Itanium 2 1.1 GHz processors joined by a
daughterboard. This new technology allows two microprocessors to occupy the same space as a
single processor. For example, a typical cell board contains four processor sockets, but with the HP
mx2 Dual-Processor Module, the same cell board can contain eight processors, resulting in double the
capacity of the system in the same chassis. The performance of the HP mx2 Dual-Processor Module is
enhanced with a 4 MB L3 cache, along with a 32 MB L4 cache.
HP Integrity rx7620-16 Server architecture
The HP Integrity rx7620-16 Server architecture is designed around the ability to operate the system as
a single 2- to 8-way (Intel Itanium 2 processor) or 2- to 16-way (HP mx2 Dual-Processor Module) SMP
server or to divide it into two independent hard partitions (nPars). Figure 6 shows the primary
components of the Integrity rx7620-16 Server architecture. When the system is configured as a non-
partitioned server, all resources shown in Figure 6 are available to perform together as one logical
server. When it is configured as two nPars, system resources are divided into two logical servers, or
independent partitions, each containing a cell board with a dedicated set of I/O resources. For
example, in Figure 6, imagine that the solid line connecting the upper and lower cell boards is no
longer there. The drawing would then reflect a system divided into two independent partitions. The
cell board, I/O bay, core I/O, and peripheral bay in the upper half of the drawing would be an
independent hard partition, which is isolated from the second partition shown in the lower half of the
drawing.