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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
Figure 6-3. Timer Clock Select Register 5 Format
Note The timer output (PWM output) cannot be used in cases where the clock is being input from an external
source.
Caution When rewriting TCL5 to other data, stop the timer operation beforehand.
Remarks 1. f
XX : Main system clock frequency (fX or fX/2)
2. f
X : Main system clock oscillation frequency
3. TI5 : 8-bit timer register 5 input pin
4. MCS : Oscillation mode selection register (OSMS) bit 0
5. Values in parentheses when operated at f
X = 5.0 MHz
0 0 0 0 TCL53 TCL52 TCL51 TCL50
76543210Symbol
TCL5
FF52H 00H R/W
Address After Reset R/W
TCL53 TCL52 TCL51 TCL50
0 0 0 0 TI5 falling edge
Note
0 0 0 1 TI5 rising edge
Note
0110
0111
f
XX/2 fX/2 (2.5 MHz) fX/2
2
(1.25 MHz)
1000
f
XX/2
2
fX/2
2
(1.25 MHz) fX/2
3
(625 kHz)
0100
0101
2f
XX Setting prohibited fX (5.0 MHz)
f
XX fX (5.0 MHz) fX/2 (2.5 MHz)
1001
f
XX/2
3
fX/2
3
(625 kHz) fX/2
4
(313 kHz)
1010
f
XX/2
4
fX/2
4
(313 kHz) fX/2
5
(156 kHz)
1011
f
XX/2
5
fX/2
5
(156 kHz) fX/2
6
(78.1 kHz)
1100
f
XX/2
6
fX/2
6
(78.1 kHz) fX/2
7
(39.1 kHz)
1101
f
XX/2
7
fX/2
7
(39.1 kHz) fX/2
8
(19.5 kHz)
1110
f
XX/2
8
fX/2
8
(19.5 kHz) fX/2
9
(9.8 kHz)
1111
fXX/2
9
fX/2
9
(9.8 kHz) fX/2
10
(4.9 kHz)
MCS=1
8-Bit Timer Register 5 Count Clock Selection
MCS=0
Other than above Setting prohibited
f
XX/2
11
fX/2
11
(2.4 kHz) fX/2
12
(1.2 kHz)