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z10 EC Performance
The performance design of the z/Architecture can enable
the server to support a new standard of performance for
applications through expanding upon a balanced system
approach. As CMOS technology has been enhanced to
support not only additional processing power, but also
more PUs, the entire server is modifi ed to support the
increase in processing power. The I/O subsystem supports
a greater amount of bandwidth than previous generations
through internal changes, providing for larger and faster
volume of data movement into and out of the server. Sup-
port of larger amounts of data within the server required
improved management of storage confi gurations, made
available through integration of the operating system and
hardware support of 64-bit addressing. The combined bal-
anced system design allows for increases in performance
across a broad spectrum of work.
Large System Performance Reference
IBM’s Large Systems Performance Reference (LSPR)
method is designed to provide comprehensive z/Archi-
tecture processor capacity ratios for different confi gura-
tions of Central Processors (CPs) across a wide variety
of system control programs and workload environments.
For z10 EC, z/Architecture processor capacity identifi er is
defi ned with a (7XX) notation, where XX is the number of
installed CPs.
Based on using an LSPR mixed workload, the perfor-
mance of the z10 EC (2097) 701 is expected to be up to
1.62 times that of the z9 EC (2094) 701.
The LSPR contains the Internal Throughput Rate Ratios
(ITRRs) for the z10 EC and the previous-generation
zSeries processor families based upon measurements
and projections using standard IBM benchmarks in a con-
trolled environment. The actual throughput that any user
may experience will vary depending upon considerations
such as the amount of multiprogramming in the user’s job
stream, the I/O confi guration, and the workload processed.
LSPR workloads have been updated to refl ect more
closely your current and growth workloads. The classifi ca-
tion Java Batch (CB-J) has been replaced with a new clas-
sifi cation for Java Batch called ODE-B. The remainder of
the LSPR workloads are the same as those used for the z9
EC LSPR. The typical LPAR confi guration table is used to
establish single-number-metrics such as MIPS and MSUs.
The z10 EC LSPR will rate all z/Architecture processors
running in LPAR mode, 64-bit mode, and assumes that
HiperDispatch is enabled.
For more detailed performance information, consult the
Large Systems Performance Reference (LSPR) available
at: http://www.
ibm.com
/servers/eserver/zseries/lspr/.
CPU Measurement Facility
The CPU Measurement Facility is a hardware facility which
consists of counters and samples. The facility provides a
means to collect run-time data for software performance
tuning. The detailed architecture information for this facility
can be found in the System z10 Library in Resource Link
™
.
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