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42 Specification Update
HSD101. Incorrect LBR Source Address May be Reported For a Transactional
Abort
Problem: If the fetch of an instruction in a transactional region causes a fault, a transactional abort
occurs. If LBRs are enabled, the source address recorded for such a transactional abort
is the address of the instruction being fetched. If that instruction was itself the target of an
earlier branch instruction, this erratum may erroneously record the address of the branch
instruction as the source address for the transactional abort
Implication: Trace reconstruction software that uses LBR information may fail when this erratum
occurs
Workaround: None identified
Status: For the steppings affected, see the Summary Table of Changes.
HSD102. Address Translation Faults for Intel
®
VT-d May Not be Reported for
Display Engine Memory Accesses
Problem: The Intel
®
VT-d (Intel
®
Virtualization Technology for Directed I/O) hardware unit
supporting the Processor Graphics device (Bus 0; Device 2; Function 0) may not report
address translation faults detected on Display Engine memory accesses when the
Context Cache is disabled or during time periods when Context Cache is being
invalidated.
Implication: Due to this erratum, Display Engine accesses that fault are correctly aborted but may
not be reported in the FSTS_REG fault reporting register (GFXVTDBAR offset 034H).
Workaround: None identified
Status: For the steppings affected, see the Summary Table of Changes.
HSD103. L3 Cache Corrected Error Count May be Inaccurate After Package C7
Exit
Problem: The corrected error count for L3 cache errors reported in IA32_MCi_STATUS.Corrected
Error Count (bits [52:38]) with an MCACOD of 0001 0001 xxxx xxxx (x can be 0 or 1) may
be incorrectly restored to a smaller value during exit from Package C7.
Implication: The corrected error count for L3 cache errors in IA32_MCi_STATUS may be inaccurate
after Package C7 exit.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD104. PCIe* Device’s SVID is Not Preserved Across The Package C7 C-State
Problem: Bus 0, Device 7, Function 0’s SVID register (Subsystem Vendor Identification, Offset
2CH) is not preserved across package C7 C-State transitions.
Implication: This may cause the operating system to think the device has been replaced with a
different device.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.