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44 Specification Update
HSD109. Processor Energy Policy Selection May Not Work as Expected
Problem: When the IA32_ENERGY_PERF_BIAS MSR (1B0H) is set to a value of 4 or more, the
processor will try to increase the energy efficiency of Turbo mode. However, this
functionality is effectively disabled if the software requested P-state exceeds the
maximum P-state supported by the processer. This has the effect of decreasing the
energy efficiency of the processor while in Turbo mode.
Implication: When this erratum occurs, reduced battery life and reduced energy efficiency may
occur.
Workaround: BIOS should set the max ACPI _PST object to the max supported turbo ratio, ensuring
that the software P-state request does not exceed the maximum ratio supported by the
processor.
Note that this workaround will disable Core Ratio Overclocking.
Status: For the steppings affected, see the Summary Table of Changes.
HSD110. A PEBS Record May Contain Processor State for an Unexpected
Instruction
Problem: If a performance counter has overflowed and is configured for PEBS (precise event-
based sampling), the processor will arm the PEBS hardware within a bounded number
of cycles called the skid (see the discussion of skid and related topics in the Precise
Distribution of Instructions Retired section of the Intel
®
64 and IA-32 Architectures
Software Developer Manual). Once the PEBS hardware is armed, the processor should
capture processor state in a PEBS record following the execution of the next instruction
that causes the counter to increment (a “triggering” instruction).
Due to this erratum,
the capture of processor state may occur at an instruction after the first triggering
instruction following the skid but not beyond the second triggering instruction after the
skid.
Implication: A PEBS record may contain processor state (including instruction pointer) not
associated with the triggering instruction.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD111. MSR_PP1_ENERGY_STATUS Reports Incorrect Energy Data
Problem: The MSR_PP1_ENERGY_STATUS MSR (641H) bits [31:0] reports incorrect energy data.
Implication: Due to this erratum, reported Intel Integrated Graphics domain energy consumption
may not be accurate.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD112. x87 FPU DP May be Incorrect After Instructions That Save FP State to
Memory
Problem: Under certain conditions, the value of the x87 FPU DP (Floating Point Unit Data Pointer)
saved by the FSAVE/FNSAVE, FSTENV/FNSTENV, FXSAVE, XSAVE, or XSAVEOPT
instructions may be incorrect.
Implication: Due to this erratum, the x87 FPU DP may be incorrect.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.