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40 Specification Update
HSD92. Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a
#NM Exception
Problem: Attempt to use FXSAVE or FXRSTOR with a VEX prefix should produce a #UD (Invalid-
Opcode) exception. If either the TS or EM flag bits in CR0 are set, a #NM (device-not-
available) exception will be raised instead of #UD exception.
Implication: Due to this erratum a #NM exception may be signaled instead of a #UD exception on
an FXSAVE or an FXRSTOR with a VEX prefix.
Workaround: Software should not use FXSAVE or FXRSTOR with the VEX prefix.
Status: For the steppings affected, see the Summary Table of Changes.
HSD93. RDRAND Execution in a Transactional Region May Cause a System
Hang
Problem: Execution of the RDRAND (Random number generator) instruction inside an Intel
®
TSX
transactional region may cause the logical processor to hang.
Implication: A system hang may occur as a result of this erratum.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD94. Uncore Clock Frequency Changes May Cause Audio/Video Glitches
Problem: On some processors, the time required to change the uncore clock frequency may be
large enough to significantly lengthen the latency of I/O Requests to memory, possibly
resulting in audio or video glitches.
Implication: Audio/Video glitches may occur during uncore ratio changes.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD95. Processor May Experience a Spurious LLC-Related Machine Check
During Periods of High Activity
Problem: Due to certain internal conditions while running core and memory intensive operations,
some processors may incorrectly report an LLC (last level cache) related machine check
with a IA32_MCi_STATUS.MCACOD value of 110AH.
Implication: Due to this erratum, the processor may experience a machine check.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD96. The Processor May Not Enter Package C7 When Using a PSR Display
Problem: The processor datasheet specifies that entering package C7 requires enabling PSR
(Panel Self Refresh) for certain display resolutions, along with other conditions.
Due to
this erratum, the processor may not enter package C7 when connected to a PSR-
enabled display even if all of the required conditions are met.
Implication: Due to this erratum, the processor may not enter package C7.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.