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Specification Update 43
HSD105. Warm Reset Does Not Stop GT Power Draw
Problem: Due to this erratum, if GT is enabled prior to a warm reset, it will remain powered after the
warm reset. The processor will make incorrect power management decisions because it
assumes the GT is not drawing power after a warm reset.
Implication: The processor may draw more current than expected from an external VR (Voltage
Regulator). The processor may also put the external VR into a low power state where it
will be unable to supply the sufficient power resulting in unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD106. Unused PCIe* Lanes May Remain Powered After Package C7
Problem: If a PCIe controller is enabled and either has unused lanes or no PCIe device is present,
the link and/or unused lanes should enter a low power state. Due to this erratum, after
exiting Package C7, the unused link and/or unused lanes may remain powered.
Implication: Power consumption may be greater than expected.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD107. BMI1 And BMI2 Instruction Groups Are Not Available
Problem: Feature flags BMI1 and BMI2 (CPUID leaf 7, sub-leaf 0, EBX bits 3 and 8) report these
two groups of bit manipulation instructions are not present for the Intel
®
Core™ i3-4330TE
but these instruction groups should be available. An attempt to execute any of these
instructions will generate a #UD fault.
Implication: Software attempting to use any of instructions in the BMI1 and BMI2 groups will result in a
#UD fault.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD108. Virtual-APIC Page Accesses With 32-Bit PAE Paging May Cause a
System Crash
Problem: If a logical processor has EPT (Extended Page Tables) enabled, is using 32-bit PAE paging, and
accesses the virtual-APIC page then a complex sequence of internal processor micro-architectural
events may cause an incorrect address translation or machine check on either logical processor.
Implication: This erratum may result in unexpected faults, an uncorrectable TLB error logged in
IA32_MCi_STATUS.MCACOD (bits [15:0]) with a value of 0000_0000_0001_xxxxb
(where x stands for 0 or 1), a guest or hypervisor crash, or other unpredictable system
behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.