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Evaluation Board for Octal E1 Applications — LXD381
Developer Manual 11
Figure 5. Evaluation Board Schematic — Digital I/O
RNEG1/BPV1
RPOS1/RDATA1
RCLK1
RNEG0/BPV0
RPOS0/RDATA0
RCLK0
TCLK1
TPOS1/TDATA1
TCLK2
RCLK3
RNEG2/BPV2
TPOS3/TDATA3
RNEG3/BPV3
TPOS2/TDATA2
RCLK2
RPOS2/RDATA2
TCLK3
RPOS3/RDATA3
TPOS4/TDATA4
TCLK4
RCLK4
RPOS4/RDATA4
RNEG4/BPV4
RNEG5/BPV5
RPOS5/RDATA5
RCLK5
TCLK5
TPOS5/TDATA5
TPOS6/TDATA6
TPOS7/TDATA7
RCLK6
RPOS6/RDATA6
RNEG6/BPV6
RCLK7
RPOS7/RDATA7
RNEG7/BPV7
TCLK7
TCLK6
TNEG0/UBS0
TNEG1/UBS1
TNEG2/UBS2
TNEG3/UBS3
TNEG4/UBS4
TNEG5/UBS5
TNEG6/UBS6
TNEG7/UBS7
TCLK0
TPOS0/TDATA0
LOS0
LOS1
LOS2
LOS3
LOS5
LOS7
LOS6
LOS4
TCLK7
TCLK5
TCLK4
TCLK6
TCLK1
TCLK2
TCLK3
TCLK0
TPOS0/TDATA0
TPOS4/TDATA4
TPOS2/TDATA2
TPOS3/TDATA3
TPOS1/TDATA1
TPOS7/TDATA7
TPOS6/TDATA6
TPOS5/TDATA5
TNEG1/UBS1
TNEG2/UBS2
TNEG5/UBS5
TNEG7/UBS7
TNEG4/UBS4
TNEG3/UBS3
TNEG0/UBS0
TNEG6/UBS6
JP3
HEADER 5X2
12
34
56
78
910
JP1
HEADER 5X2
12
34
56
78
910
JP5
HEADER 5X2
12
34
56
78
910
JP7
HEADER 5X2
12
34
56
78
910
JP2
HEADER 5X2
12
34
56
78
910
JP4
HEADER 5X2
12
34
56
78
910
JP6
HEADER 5X2
12
34
56
78
910
JP8
HEADER 5X2
12
34
56
78
910
RN3
R.NETWORK 100K
10
2
1
3
4
6
7
8
9
5
CM1
R2
R1
R3
R4
R5
R6
R7
R8
CM2
RN4
R.NETWORK 100K
10
2
1
3
4
6
7
8
9
5
CM1
R2
R1
R3
R4
R5
R6
R7
R8
CM2
RN5
R.NETWORK 100K
10
2
1
3
4
6
7
8
9
5
CM1
R2
R1
R3
R4
R5
R6
R7
R8
CM2
CHANNEL 1
CHANNEL 0
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7